1. Field of the Invention
The invention relates to an analog/digital converter and to a method for converting an analog signal into a digital signal.
Analog/digital converters (ADCs) are produced on the basis of the prior art as an integrated circuit utilizing metal oxide semiconductor structures and/or bipolar semiconductor structures on semiconductor substrates as standard. With high demands on the signal processing speed, so called xe2x80x9cflash ADCsxe2x80x9d are frequently reverted to.
2. Description of the Related Prior Art
As FIG. 1 shows, a flash ADC based on the prior art is an analog/digital converter 101 which has, by way of example, a resistor cascade containing a plurality of series-connected resistors 102 and a plurality of comparators 103, with a first input 104 on the comparators 103 being connected between two respective adjacent resistors 102, as a reference network. A reference voltage Uref is applied to the resistor cascade between the cascade input 105 and the ground connection 106 such that the reference voltage Uref drops in partial voltages between the resistors 102. These partial voltages are evaluated by a respective one of the comparators 103. To make illustration clearer, FIG. 1 shows just three comparators 103, but the flash ADC can have any number of comparators 103.
An analog signal to be converted, i.e. an analog voltage Ua, is applied via an analog signal input 107 to a second input 108 on all the comparators 103 in parallel. The comparators 103 then compare the analog voltage Ua applied to the second input 108 with the respective partial voltage applied to the first input 104. If the analog voltage Ua applied to one of the comparators 103 is higher than the partial voltage applied, then the comparator 103 has been activated and outputs at an output 109 a bit signal which corresponds to a first bit value xe2x80x9c1xe2x80x9d, otherwise the bit signal corresponds to a second bit value xe2x80x9c0xe2x80x9d.
Finally, a digital evaluation unit 110 produces a digital output signal D in line with the comparator 103 activated with the highest partial voltage, and outputs this signal at a digital signal output 111.
FIG. 1 shows, in each of the comparators 103, a graph 112 plotting a probability density dW against a voltage difference xcex94U. In this case, dW denotes the probability density of there being a change from a first bit value xe2x80x9c1xe2x80x9d to a second bit value xe2x80x9c0xe2x80x9d or vice versa for the indicated input difference voltage xcex94U at the output 109 of the respective comparator 103. An ideal comparator has an infinitesimally narrow probability density dW, i.e. the change from one bit value to the other bit value takes place exactly at the input difference voltage xcex94U=0. On account of statistical effects, real comparators have a broad probability density dW, however. By way of example, the result of this is that the comparator 103 would (not) be activated even though an analog voltage Ua which is (higher) lower than the applied partial voltage is applied. The voltage difference xcex94U plotted in the graph 112 is formed from the applied partial voltage of the reference voltage Uref and the applied analog voltage Ua.
FIG. 2 shows a graph 201 plotting a curve 202 for the response probability density 203 of comparators 103 in the flash ADC described in FIG. 1 against the applied analog voltage Ua 204. The graph 201 results from a combination of the individual probability densities dW of the comparators 103, which are shown in FIG. 1 as individual graphs 112 in the comparators 103.
Since each comparator 103 is associated with a different portion of the reference voltage Uref, the curve 202 for the response probability density 203 of the comparators 103 is obtained from a linear plot of the individual probability densities dW of adjacent comparators 103 in a rising direction against the applied analog voltage Ua 204. The result of the virtually isolated probability densities dW of the individual comparators 103 is that the changes in the comparators 103 are very precisely defined and the flash ADC thus has a high level of accuracy. On the basis of the prior art, flash ADCs are produced with accuracies of typically 5 to 6 bits and are used, inter alia, in the read paths of hard disks.
A commonly used analog/digital converter normally involves the use of resistors for producing the reference values, which are produced on the semiconductor substrate from a semiconductor material, each corresponding resistance value being determined by the number of atomic, molecular and crystallite boundaries in the semiconductor material within the respective resistance area A.
If the resistance area A is reduced, the atomic, molecular or crystallite number in the semiconductor crystal falls, and hence the number of atomic, molecular and crystallite boundaries falls, as a result of which the standard deviation of the resistance value corresponding to this resistance area A increases by the factor ({square root over (A)})xe2x88x921. If the resistance area A decreases, the probability W that a comparator has been activated and outputs an incorrect bit signal, even though an analog voltage Ua is applied which is lower than the reference network""s nominal partial voltage applied to the comparator in question, thus increases.
The accuracy of such an analog/digital converter is also determined by the statistical fluctuations in the transistor parameters. By way of example, the variation in the threshold voltage of an MOS transistor likewise decreases by a factor of ({square root over (A)})xe2x88x921 as the area of the transistor increases. This parameter variation in the comparator""s transistors results in the xe2x80x9cinput offset voltagexe2x80x9d, so that a comparator does not turn round at an input voltage difference xcex94U of exactly xcex94U=0, but rather at an input voltage difference xcex94U which corresponds to the individual comparator offset.
These statistical variations limit the linearity of the overall analog/digital converter system, which is why the design needs to take into account sufficient component areas in order to satisfy the demands on accuracy.
If the individual comparators have sufficient accuracy, then a chain of comparators connected to a resistor network in the manner described above has an output signal which is known as a thermometer code. This means that all the comparators whose first input is connected to a partial voltage of the reference voltage Uref which is lower than the analog voltage Ua applied to the second input output the bit value xe2x80x9c1xe2x80x9d, whereas all the other comparators output the bit value xe2x80x9c0xe2x80x9d. Such output signals can then be converted particularly easily into a digital output word. Normally, a thermometer binary coder and the outputs of the comparators also have a correction logic unit connected between them, said correction logic unit eliminating so called xe2x80x9cbubblesxe2x80x9d in the thermometer code (a xe2x80x9c0xe2x80x9d between a plurality of xe2x80x9c1xe2x80x9ds and vice versa) in order to permit reliable binary coding.
The resistor network described above in connection with the flash ADCs is used for providing reference partial voltages with which an analog input voltage Ua is compared in the comparators. Alternatively to the resistor networks, any other reference signal network can also be used. Thus, by way of example, it is also possible to use current sources having different output currents as a reference signal. The information-bearing variable used can thus be not just voltages, but rather xe2x80x9ccurrent-modexe2x80x9d solutions are also possible, which involve the information being represented by currents.
In contrast to the parameter variations, the parasitic capacitances which arise for relatively large component areas and are generally unwanted increase as the component area A increases. As a result, the signal processing speed decreases, however. This therefore means that a high level of accuracy in a commonly used analog/digital converter is to the detriment of the signal processing speed. On the basis of the prior art, flash converters in CMOS technology with conversion rates of up to 1 Gsa/s (giga samples per second=109 sampling operations per second) are produced with an accuracy of 6 bits.
In addition [1] describes an analog/digital converter with a reference network, a multiplicity of comparators and an interpolation unit. The interpolation unit comprises a multiplicity of additional comparators to which the output signals from the comparators in a first stage, which are connected directly to the reference network, are supplied following weighting of the output signals. The additional comparators thus serve as an interpolation unit for interpolating the signals provided by the comparators in the first stage.
The interpolation network described in [1] is used merely for recoding the information from the thermometer code into the binary code, with deterministic signal processing being performed continuously.
Another analog/digital converter having an interpolation network is described in [2].
The invention is thus based on the problem of specifying an analog/digital converter and a method for converting an analog signal into a digital signal which allow a high level of accuracy and linearity to be achieved for the converter despite a small component size.
The problem is solved by an analog/digital converter and by a method for converting an analog signal into a digital signal having the features based on the independent patent claims.
An analog/digital converter has a plurality of comparators and a reference network, the reference network having a plurality of reference elements. Connected between each reference element in the analog/digital converter""s reference network is at least one input of at least one comparator. The outputs of the comparators in the analog/digital converter have a digital evaluation circuit coupled to them which can be used for statistically processing output signals produced by the comparators.
A method for converting an analog signal into a digital signal involves a reference signal being applied to a reference network having a plurality of reference elements, and an analog signal being applied to at least one input of a plurality of comparators. With this method, the comparators, at least one further input of which is connected to the reference network, form a plurality of digital output signals which are subsequently processed statistically. The method according to the invention finally also involves a common digital signal being formed from the statistically processed output signals.
One advantage of the invention can clearly be seen in that the problem of the component mismatch is taken into account by virtue of a simple circuit being used to performxe2x80x94erroneousxe2x80x94quantization very early in the analog signal path, and then statistical processing in the digital part of the analog/digital converter taking place. To this end, a large number of comparators having very small component areas and therefore poor accuracy are clearly used, and their digital outputs are counted using a suitable logic unit and are thereby averaged, for example.
Another advantage of the analog/digital converter according to the invention is its suitability for very low operating voltages. Since the proportion of the analog components in the analog/digital converter according to the invention is very small and the analog components also end up being very simple, the ratio of operating voltage to threshold voltage, from which point on a change can be detected in a comparator, for example, can be kept very low. This means that the analog/digital converter according to the invention is also suitable for use in novel integrated circuits having a low operating voltage.
Finally, another advantage which arises is that the digital part of the analog/digital converter according to the invention can be produced largely automatically by virtue of program/controlled activation of existing integrated circuits (VHDL=very high speed IC hardware description language). This significantly reduces the design complexity, and hence the manufacturing complexity, and also the manufacturing costs. In addition, simple portability to new technologies is ensured.
As reference network, the use of a resistor network, a current-source network or a capacitive network is preferred. Reference elements used are then resistors, current sources or capacitors.
Preferably, the digital evaluation circuit in the analog/digital converter according to the invention is set up such that the statistical processing of the output signals can involve formation of a statistical mean.
Alternatively, the statistical processing could also comprise filtering of the output signals in order to mask out digital outlier output signals, weighting of the output signals relative to the center of an output-signal cluster, or any other type of statistical signal processing. One advantage of statistical processing is the improvement in the accuracy of the analog/digital converter.
In one preferred embodiment of the analog/digital converter according to the invention, a plurality of comparators are connected in parallel between each reference element in the reference network, and the digital evaluation circuit is set up such that the statistical processing can involve the output signals produced by parallel comparators being averaged and a common output signal being formed therefrom.
In another preferred embodiment of the analog/digital converter according to the invention, a comparator having a plurality of outputs which are activated at different input difference voltages is connected between each reference element in the reference network. The digital evaluation circuit is set up such that the statistical processing can involve the output signals produced by the comparators being averaged and a common output signal being formed therefrom.
In another preferred embodiment of the analog/digital converter according to the invention, a plurality of comparators are grouped into a plurality of groups, and the digital evaluation circuit is set up such that the statistical processing can involve the output signals produced by the comparators in a respective group being averaged and a common output signal being formed therefrom.
In one preferred embodiment of the analog/digital converter according to the invention, fully differential signal processing is used. The analog input voltage Ua and the reference voltage Uref are in the form of differential signals and are evaluated in comparators having at least two reference signal inputs and at least two measuring signal inputs.
The method according to the invention preferably involves the digital output signals being grouped into a plurality of signal groups containing a plurality of digital output signals. Accordingly, the statistical processing of the digital output signals is performed within the respective signal group.
Preferably, the method according to the invention involves the statistical processing performed being formation of a statistical mean for the digital output signals. This can be achieved, by way of example, by a 1-bit adder having n inputs when n outputs of comparators are available. With 255 adder inputs which can each take the bit value xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, this results in an output word having the length of 8 bits.
Exemplary embodiments of the invention are illustrated in the figures and are explained in more detail below. In this case, identical references denote identical components.